Three-dimensional integrated circuits (3D-ICs) have emerged as a promising solution to extend the 2D scaling trajectory predicted by the Moore's Law. Currently, through-silicon vias (TSVs) are used in the formation of 3D-ICs to allow vertical stacking of multiple dies fabricated separately. However, the quality of TSV-based 3D-ICs strongly depends on dimensions of TSVs and parasitic elements, and are limited to memory-on-logic or large logic-on-logic designs with relatively small number of global interconnects.
An emerging alternative to TSV-based 3D-ICs is monolithic 3D-ICs (also known as “M3D”). Monolithic 3D-IC technology involves sequential fabrication of two or more tiers of devices, instead of bonding two previously fabricated dies using micro bumps.
Monolithic 3D-ICs enable integration densities which are orders of magnitude higher than that of (TSV)-based 3D-IC technology. This is due to the fact that monolithic 3D-ICs utilize extremely small monolithic inter-tier vias (MIVs). Overall, MIVs provide better electrical characteristics (i.e., less parasitics, electrical coupling, etc.) than TSVs, and also enable higher integration densities due to their small size.
However, monolithic 3D-ICs face challenges when it comes to power delivery. The packed integration of tiers of devices in monolithic 3D-ICs leaves very little room for integration of power delivery networks (PDNs). Accordingly, effective solutions for integration of PDNs in monolithic 3D-ICs are needed.